The present invention relates to a memory access control unit and, more particularly, to a memory access control unit which is capable of limiting processing of an instruction processor (IP) request thereby preventing generation of channel overrun of an input-output processor (IOP) when the IOP is transferring data at maximum throughput.
As to a conventional memory access control unit, the control of processing of a request from an IOP is utilized in some units as a countermeasure to channel overrun as disclosed in JP-A-57-205882.
In the case of this control unit, when required data does not exist on a buffer memory, a fetching operation by the IOP under a specific condition from an input-output channel for instance, required data is loaded in the buffer memory from a main memory. Otherwise, the buffer memory is not accessed, but the main memory is accessed directly.
In above-described prior art, however, no consideration is given to the handling of a request of the IP when the IOP is transferring data at the maximal, or maximum, throughput. In a multiprocessor system, request processing capacity of a system control unit (SCU) is increased. Accordingly, the request from the IP is also received when the IOP is transferring the data at the maximal throughput. As a result, throughput is lowered. Particularly in a system having a cache memory in the SCU, when data that does not exist in the cache memory is accessed by the request from the IP, a long cycle is occupied for processing that request, which causes lowering of the throughput of the IOP.